Position Summary

Role and Responsibilities

- Low Jitter and high frequency PLL Design Experience . Both LC and Ring based PLL deisgn Experience

- General Purpose ADC and thermal Senors IP deisgn Experience

- High speed Serdes Design Experience.

- LDO , BGR and other Power managemnt blocks.

Ideal Candidate should  be ready for challenging deisgn experince and exposure to silion validation . He will get full exposure to IP deisgn cycle in advanced samsung foundry process 4nm and below.

Skills and Qualifications

B.Tech/M.Tech / PHd

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