Position Summary

Role and Responsibilities

• 10 to 15 years of work experience in VLSI SoC RTL design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock/reset, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU, Host Subsystem, Flash Subsystem.

  
  
  

• Understanding of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and AHB.

  
  
  

• Creating micro-architecture and detailed design documents for SoC design keeping in mind performance, power, area requirements.

  
  
  

• Strong debugging skills and very good experience in DV tools like Verdi, NCSIM.

  
  
  

• SOC Integration experience preferred of Top Level, Block Level or Subsystem level.

  
  
  

• Working with DV team to enable verification coverage improvement. Working on GLS closure with DV, PD and Modelling team.

  
  
  

• Must have knowledge in clock domain crossing (CDC), Linting, UPF.

  
  
  

• Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc. is a must.

  
  
  

• Understanding and defining constraints and critical high speed path timing closure working with back end teams

  
  
  

Skills and Qualifications

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